The present invention relates to multiprocessor systems, and more particularly to performing a speculative request in a cache coherent multi-core microprocessor system.
Advances in semiconductor fabrication technology have given rise to considerable increases in microprocessor clock speeds. Although the same advances have also resulted in improvements in memory density and access times, the disparity between microprocessor clock speeds and memory access times continues to persist. To reduce latency, often one or more levels of high-speed cache memory are used to hold a subset of the data or instructions that are stored in the main memory. A number of techniques have been developed to increase the likelihood that the data/instructions held in the cache are repeatedly used by the microprocessor.
To improve performance at any given operating frequency, microprocessors with a multitude of cores that execute instructions in parallel have been developed. The cores may be integrated within the same semiconductor die, or may be formed on different semiconductor dies coupled to one another within a package, or a combination of the two. Each core typically includes its own level-1 cache and an optional level-2 cache.
In order to reduce the average latency associated with a coherent read request, a technique commonly referred to as speculative read may be used. In accordance with this technique, concurrently with searching for the requested data in the caches, a speculative read request is also issued to the memory. If the requested data is stored in any of the caches, the speculative read is cancelled. If the requested data is not stored in any of the caches, the speculative read is confirmed and the data identified by the confirmed request is transferred from the memory to the requesting core.